The present invention relates to a reference voltage generating circuit including CMOS transistors for compensating the reference voltage output for variations of temperature and the external source voltage level.
The miniaturization of semiconductor memory devices of high complexity requires a reference voltage generating circuit for supplying an internal reference voltage lower by a given value than an external source voltage. In this connection, it is required that the reference voltage generating circuit provide a stable reference voltage regardless of variations of environmental temperature, external source voltage, process parameters, etc. To this end, there has been proposed a band-gap reference voltage generating circuit as shown in FIG. 1.
With reference to FIG. 1, the proposed band-gap reference voltage generating circuit includes first, second, and third bipolar transistors 14, 20 and 22, respectively, supplied with a current via a current supply resistor 24. The first transistor 14 has a diode-connected collector-base and is connected between a reference voltage terminal Vref and a ground voltage terminal Vss. The second transistor 20 has a base connected through a node 12 to the collector of the first transistor 14, a collector connected through a resistor 16 to the reference voltage terminal Vref, and an emitter connected through a resistor 21 to the ground voltage terminal Vss. The proposed band-gap reference voltage generating circuit also includes a resistor 10 connected between the node 12 and the reference voltage terminal Vref.
The third transistor 22 has a collector connected to the reference voltage terminal Vref, an emitter connected to the ground voltage terminal Vss, and a base connected to the collector of the second transistor 20. This circuit causes the base-emitter voltage (.differential.V.sub.BE /.differential.T.congruent.-2.2 mV/.degree.C.) with a negative thermal coefficient to counterbalance the thermal voltage (V.sub.T =Kt/1, .differential.Vt/.differential.T =0.086 mV/.degree.C.) with a positive thermal coefficient in order to generate a stable reference voltage output with respect to temperature variations. More particularly, the reference voltage Vref is the sum of the voltage V1 across the resistor 16 and the base-emitter voltage V.sub.BE22 of the third transistor 22. The voltage V1 depends on the variation .DELTA.V.sub.BE20 of the base-emitter voltage of the second transistor 20. Assuming that the resistors 16 and 21 are respectively R16 and R21 and that the currents passing through the resistors 21 and 10 are respectively I1 and I2, Eqs. (1) and (2) may be obtained as follows: EQU .DELTA.V.sub.BE20 =I1.multidot.R21=V.sub.BE14 -V.sub.BE20 =V.sub.T 1n(I2/I1)(1) EQU V1=(R16/R21).multidot..DELTA.V.sub.BE20 =V.sub.T .multidot.(R16/R21)1n(I2/I1) (2)
where, V.sub.T (=kt/q) is the thermal voltage with a positive thermal coefficient, k is the Boltzman constant, T is the absolute temperature, and q is the charge quantity. Hence, the reference voltage Vref is determined by the base-emitter voltage V.sub.BE22 of the third transistor 22 with the negative thermal coefficient and the thermal voltage V.sub.T with the positive thermal coefficient, as expressed by the following Eq. (3). EQU Vref=V.sub.BE22 +V.sub.T (R16/R21) (3)
Thus, the reference voltage Vref is stabilized with respect to temperature variations. Moreover, the bipolar transistors work depending on the relatively stable base-emitter voltage V.sub.BE22 of the third transistor 22, which is operated in its saturation region, thereby providing a relatively stable reference voltage with respect to variations of the external source voltage.
However, dynamic random access memory devices (DRAMs) which employ the above-described bandgap reference voltage generating circuit require a back bias generator to supply a negative substrate voltage V.sub.BB, in order to stabilize the substrate voltage. The back bias generator works only when the substrate voltage V.sub.BB exceeds a given value. The substrate voltage V.sub.BB is undesirably transferred via the polysilicon resistors of the band-gap reference voltage generating circuit and parasitic capacitances formed in the substrate to the respective circuit connections, thus varying the reference voltage output Vref. Moreover, the transistors used in the circuit operate in a saturation mode, thus undesirably increasing the standby current. In addition, if the band-gap reference voltage generating circuit is used in a DRAM device, an additional processing step for forming the bipolar transistors is required. Further, as shown by curve 112 in FIG. 6, the band-gap reference voltage generating circuit has a high set-up voltage (about 2.5 V) and exhibits large fluctuations of the reference voltage with respect to temperature variations, at low external source voltage levels.
FIG. 2 depicts another conventional reference voltage generating circuit, which includes a plurality of PMOS transistors 26, 28, 32, 34, 36, 40, and 42. The PMOS transistors 26, 28 and 32 are connected in series and each have diode-connected gates and drains, thereby producing the threshold voltage Vtp of the PMOS transistor 32 at node 30. The PMOS transistors 40 and 42 are connected in series and each have diode-connected gates and drains, thereby producing the output reference voltage 2Vtp at the reference voltage terminal 38. The voltage Vtp at the node 30 is applied to the gates of the PMOS transistors 34 and 36 which are connected in series, to thereby stabilize the reference voltage with respect to external source voltage variations. However, this reference voltage generating circuit does not compensate for variations of the reference voltage due to temperature variations.